Computer memories, such as static random access memories (SRAMs), include large arrays of physical memory cells. In the manufacture of chips bearing large arrays of physical memory cells, a very large percentage, if not all, of the chips will have a defect in at least one of the memory cells. A defect in at least one of the cells is unacceptable. In the past, for SRAMs, it has been impractical to discard all but those chips that contain no defective cells. In DRAMs, which are generally much larger arrays, discarding all chips with defects results in unacceptably low yields. As a result, memories are manufactured with both a main memory and a spare memory. The spare memory is specifically provided to replace defective memory cells in the main memory.
In a conventional memory, all of the cells on a single chip are disposed in a single block memory array. Devices for accessing the cells are arranged on two sides of the block memory array. For example, FIG. 1 depicts a prior art memory 10 including block memory array 12. Memory 10 may be a 64 K memory having 512 rows by 128 columns of cells. The rows are selected by block row decoders 14, physically located on one side of block memory array 12, adjacent the ends of the row lines. Each row line is electrically connected to block row decoders so that appropriate signals can be received and transmitted. The columns arc connected to 8 input/outputs through a series of devices. At the end of each column line, there are line precharges 16, corresponding in size, in bits, to the number of columns. Physically adjacent line precharges 16, and appropriately electrically connected, are read/write multiplexers 18. In the example of FIG. 1, with a block memory array 12 having 128 columns, there are eight 16 channel read/write multiplexers 18. Adjacent read/write multiplexers 18 are column decoders 19 and read/write circuits 20, which are electrically connected to input/outputs (not shown). Block controls 22 are located along an edge of the line precharges, the multiplexers, and the column decoders and read/write circuits, and along an edge of the block row decoders, to provide appropriate controls.
Conventionally, when a bad cell is detected, physical connections are laser burned for the row and column lines from the bad cell to a cell in a spare memory block.
In an application filed simultaneously herewith, a method and system have been developed for avoiding the need for creating physical connections. Rather, a look up table is maintained with the address of each bad cell, and a corresponding address of the corresponding cell in the spare memory block.